Raspberry Pi Zero 3 W Appears in Kernel Tree With a Pi 4 Processor

A pull request merged on October 25, 2026 into Raspberry Pi's official Linux kernel tree adds device-tree files for a Raspberry Pi Zero 3 W and a Raspberry Pi 4 Model A. The Zero 3 W file names the Broadcom BCM2711, the quad-core Cortex-A72 system-on-chip used in the Pi 4, as its processor. Raspberry Pi has not announced either board.

What the merged pull request contains

The change is raspberrypi/linux pull request 7711, titled "Add device tree for Pi Zero 3 W and Pi 4A." It was opened on October 23 by a contributor named Marta Momotko and merged two days later by Phil Elwell into the rpi-6.18.y branch. The pull request body reads "No description provided."

It holds five commits. Two of them change GPIO interrupt handling for BCM2711 pins 54 to 57 in the pinctrl: bcm2835 driver and in the ARM device-tree sources; the other three add the two board files and merge the branch. Phoronix, which reported the merge on October 27, found little else in the Zero 3 W file: "Nothing else yet too revealing about the Raspberry Pi Zero 3 W in that DT addition."

What the files say about the Zero 3 W

The developer behind the blog bret.dk read the two files line by line and published an interpretation on October 27, updated October 28. He flags that his reading comes from device trees, not a spec sheet.

The current Zero 2 W uses the RP3A0, a quad-core 1 GHz Cortex-A53. The Zero 3 W file swaps in the BCM2711, a Cortex-A72 part. The device tree gives no clock speed, so the number a buyer would want, performance against the Zero 2 W, cannot be derived from it.

The rest is a list of small signals:

• One HDMI output, with the second HDMI controller disabled.
• SPI flash lines that point to an EEPROM bootloader like the Pi 4's; the Zero 2 W has none.
• A power button on GPIO 46, mapped to KEY_POWER, and a single ACT LED.
• A four-lane camera (CSI) configuration, against two lanes on the Pi 4 Model B.
• A 40-pin GPIO header layout, which suggests existing HATs would fit.

The file also carries a storage comment mentioning an eMMC or SD card on an 8-bit bus. He reads that as a likely leftover and expects microSD, and he spots a duplicated PWR_GPIO line name that looks like a copy-and-paste artifact.

The Pi 4 Model A is a subtraction

The second file describes a Pi 4 with parts removed. Ethernet is not enabled and the PHY's GPIO lines are reused. There is one HDMI output where the Model B has two micro HDMI ports, no 3.5 mm audio or composite, and microSD with 1.8 V signalling for UHS modes. Antenna-control lines (ANT_CTRL1, ANT_CTRL2) and overlay parameters ant1, ant2 and noant resemble the onboard-or-external antenna switch on the Compute Module 4.

bret.dk's comparison, with his interpretation marked as inference, is below.

Feature	Zero 3 W	4 Model A	4 Model B
HDMI	1	1	2 micro
Ethernet	No	No	Gigabit
3.5 mm audio and composite	No	No	Yes
Power button	Yes (inferred)	Yes (inferred)	No

The number that matters here is not the clock speed but the price. The BCM2711 is probably a costlier part than the RP3A0, and bret.dk expects the Zero 3 W to cost more than the Zero line has. That is a projection from a chip choice, not a figure from Raspberry Pi, and nothing in the kernel tree states a price.

What is still unknown

Device trees describe wiring, not memory. No RAM configuration, price, clock speed, connector type or release date appears in either file. Raspberry Pi has published nothing to confirm the boards.

What would change this read: an official product page listing a different SoC would mean the files describe a prototype. Until then the pull request is the only primary document, and it is a short one. For how embedded compute is being priced elsewhere, see Omron's purchase of OnLogic at the industrial end, and Teradyne's tie-up with Sereact for who buys compute in robots.