Intel Built a GPU Around Tokens Per Watt, Then Published No Tokens Per Watt

Intel spent its Hot Chips 2026 slot describing Crescent Island, a data centre GPU it says is designed for tokens per watt. It did not publish a tokens-per-watt figure. It also did not publish the memory bandwidth.

Those two omissions are the most informative part of the disclosure, because Intel is competing on a metric it has not measured in public, using a memory technology whose weakness is the number it withheld.

What Intel did put on the slide

The reference card is a 350W air-cooled PCIe 5.0 x16 part carrying 160GB of LPDDR5X. Intel's design allows ODM partners to build versions up to 480GB. Inside are 32 Xe cores, arranged as four slices of eight, and 256 Xe Matrix Extension engines, which Intel describes as expandable from four-deep to sixteen-deep systolic arrays.

Data type support runs from FP4 and microscaling formats up to full-rate FP64, at 64 fused multiply-add operations per core. Intel has said customer sampling is planned for the second half of 2026 and has not given a general availability date.

Against Intel's own Gaudi 3 PCIe card, the capacity and power numbers are favourable: 160GB against 128GB, at 350W against 600W.

The number Intel did not print

Gaudi 3's memory bandwidth is public at 3.7TB/s. Crescent Island's is not disclosed, and two separate write-ups of the Hot Chips session flag its absence rather than reporting a figure.

This matters because of what LPDDR5X is. It is dense, cheap per gigabyte and power-efficient, which is how a 480GB card fits in an air-cooled 350W envelope. It is not fast. Nvidia's and AMD's current flagships pair far less capacity with HBM at bandwidths an order of magnitude higher.

Inference has two phases with opposite appetites. Prefill, where the model reads the prompt, is compute-bound and rewards arithmetic throughput. Decode, where it emits tokens one at a time, is bandwidth-bound: every generated token requires reading the model weights and the key-value cache again. A card with abundant capacity and modest bandwidth will hold an enormous context and then generate through it slowly.

Intel's materials describe Crescent Island as prefill-optimised. That is consistent with the memory choice, and it is also an admission about which half of the workload the part is built for.

Why capacity is the pitch

Intel's framing is agentic inference: multi-step agents that call a model repeatedly, use tools between calls, and accumulate long contexts. The design concerns Intel listed are memory capacity, KV-cache-aware routing and prefill optimisation.

That workload does stress capacity in a way that single-shot chat does not. An agent resuming a session needs its key-value cache resident, and cache that does not fit in memory has to be recomputed or paged, both of which cost more than holding it.

So the argument is coherent: for workloads whose binding constraint is how much state you can keep resident per watt, a 480GB card at 350W may beat a faster card that cannot hold the working set. The argument is also unproven, because Intel has published no measurement of it.

The software list is the other half of the claim

Intel listed Triton, SYCL-TLA, oneCCL, oneDNN, SYCL and Level Zero with an OpenCL compute runtime, plus support for vLLM, SGLang, llm-d and Nvidia Dynamo.

Naming Dynamo, Nvidia's own inference serving stack, is the more telling entry. Intel is not asking operators to port to an Intel-native serving layer. It is saying the card slots under the software they already run, which is the objection that has sunk previous non-Nvidia accelerators more often than raw performance has.

The 480GB card is not Intel's card

The capacity figure doing the work in the headlines belongs to a product Intel is not shipping. Intel's own branded card carries 160GB. The 480GB configuration is what the design permits ODM partners to build.

That distinction decides who carries the risk. An ODM building a 480GB card is committing to a memory bill of materials three times Intel's reference design on a part with no published bandwidth figure and no independent benchmarks, for a workload profile that is itself new. Partners took that bet on Gaudi and the volumes did not follow.

It also means the comparison most readers will make, 480GB against a 192GB HBM part, is between an Intel design and an Nvidia product. One of those you can buy.

Full-rate FP64 on an inference part

One specification sits oddly with the rest. Crescent Island supports full-rate FP64 at 64 fused multiply-add operations per core.

Double precision is a high-performance computing feature. Inference does not use it, and the industry has spent three years moving in the opposite direction, towards FP8 and FP4, which Crescent Island also supports. Carrying full-rate FP64 costs die area that an inference-only part would spend on something else.

The most economical reading is that Crescent Island is not an inference-only design, and that the Xe3P intellectual property underneath it is meant to serve technical computing as well. That is a reasonable engineering decision. It is not the decision implied by a pitch built entirely around tokens per watt.

What would settle it

One published figure would resolve most of this: memory bandwidth. It determines decode throughput, and decode throughput plus power is tokens per watt, the metric Intel chose to be judged on.

Until then the disclosure supports a narrower claim than the framing implies. Crescent Island is a high-capacity, low-power, prefill-oriented inference card whose generation speed is unstated. Whether that is the right trade depends entirely on the ratio of prefill to decode in a given deployment, which varies by more than an order of magnitude between a document-analysis pipeline and a chat product.

Sampling in the second half of 2026 means the first independent numbers will come from customers, not from Intel. Those are the numbers worth waiting for.

Related: Anthropic's four breaking API changes and the vendor-supplied scores behind GPT-6 Astra, both cases of a vendor choosing which figures to publish.