OpenAI's Jalapeño Chip Claims Hide an Unequal Test

OpenAI's Jalapeño inference chip went from first architecture concept to first silicon in under 20 months, with only nine months between the first RTL and tape-out, IEEE Spectrum reported Sept. 14. The number that matters more than the timeline is the asterisk EE Times found in OpenAI's own benchmark disclosure: the chip's reported 1.5-to-4.1-times efficiency gains over comparable systems compare OpenAI's single-token prediction against rivals that are typically measured with speculative multi-token prediction switched on, an optimization that alone is worth another 3 to 5 times.

OpenAI built Jalapeño with Broadcom, which handled backend design from the gate level onward, and manufacturing partner Celestica. The company received its first chips in May 2026, according to IEEE Spectrum, and Richard Ho, OpenAI's vice president of hardware, said small-volume deployments are planned for the end of 2026 with a larger ramp in 2027, focused first on low-latency workloads such as code generation.

What Jalapeño is, and when it shipped

Jalapeño delivers 13.4 petaflops of 4-bit compute, 232 gigabytes of HBM4 memory, and 15.4 terabytes per second of memory bandwidth, drawing roughly 700 watts per accelerator, according to IEEE Spectrum's reporting. OpenAI designed the chip around tight coupling between HBM banks and compute cores to minimize data movement, a clean-sheet architecture rather than a derivative of an existing accelerator line.

Spec	Jalapeño
Compute	13.4 petaflops (4-bit)
Memory	232 GB HBM4
Bandwidth	15.4 TB/s
Power	~700 W per accelerator
Concept to first silicon	Under 20 months
RTL to tape-out	9 months

The AI-assisted design timeline

OpenAI said it used its own models, including o3 and precursors to GPT-6 Astra, to accelerate chip design work carried out by a team that has averaged fewer than 100 people. The company built its front-end design flow around Google's open-source XLS high-level synthesis toolchain, letting engineers write DSLX and C++ that XLS converts to Verilog, on the theory that current models perform better on software-like code than on raw hardware description languages.

OpenAI Member of Technical Staff Chris Leary said the team was "thinking about how to leverage AI to make the project faster, and the AI was much better at software-looking things." One resulting benchmark: an AI-guided optimization pass took a DeepSeek multi-head latent attention kernel from 0.31 percent to 88.94 percent of its theoretical performance ceiling in about 40 hours, and a separate AI-guided physical-design pass cut the area of the chip's matrix-multiplication unit by 10 percent against an optimized human baseline. Ho said the models are "giving superpowers to our engineers," while also saying chip design cannot be fully automated and still requires specialized, focused teams.

The benchmark numbers, and the asterisk EE Times found

OpenAI's own InferenceX benchmark results, which The Terminal has not independently verified, claim 1.5 to 1.9 times more AI work per watt, 1.7 to 3.6 times lower end-to-end latency, and 2.1 to 4.1 times higher performance on interactive workloads, tested against comparable systems running OpenAI's GPT-OSS-120B, Moonshot AI's Kimi K2.5 1T and DeepSeek's R1 670B, according to EE Times.

1. AI work per watt1.5 x
2. Lower end-to-end latency1.7 x
3. Interactive workload performance2.1 x

Source: EE Times, accessed 2026-09-19

EE Times reported the catch: OpenAI measured Jalapeño using single-token prediction without speculative multi-token prediction, while the competing systems OpenAI compared it against are commonly benchmarked with multi-token prediction enabled, a technique that on its own typically delivers a 3-to-5-times performance boost. That means the low end of OpenAI's own range, a 1.5-times efficiency gain, could just as easily reverse into a deficit once both sides are measured on the same optimization setting, a comparison neither OpenAI nor EE Times has published.

EE Times also reported that OpenAI's team brought up three separate large language models on Jalapeño silicon within about two months of receiving the chips, and that OpenAI Chief Financial Officer Sarah Friar has framed the project around internal use rather than external sales, since the company says its own inference demand already exceeds what it can buy on the merchant market. That framing matters for how to read the benchmark: a chip built to satisfy internal demand has less commercial pressure to publish a number that would survive a hostile third-party rerun than one built to be sold against Nvidia's GB300 in an open market.

Why the design-cycle claim matters more than the benchmark

If OpenAI's nine-month RTL-to-tape-out cycle generalizes rather than reflecting one well-resourced project, the second-order effect is on every other lab's build-versus-buy math, not just OpenAI's. A shorter design cycle lowers the fixed cost of a custom accelerator, which lowers the inference volume at which building silicon beats renting it, the same volume threshold that determines whether a lab buys another generation of merchant GPUs or spins up its own line, a decision Alibaba's Qwen team faces from the opposite direction as it optimizes models to fit onto hardware it does not control.

What would change this read

A published Jalapeño benchmark with multi-token prediction enabled on both sides, or an independent lab reproducing the InferenceX numbers, would settle whether the 1.5-to-4.1-times range survives an apples-to-apples comparison. Until then, the more durable claim in this release is the design-cycle one: Intel's Crescent Island shipped with no tokens-per-watt figure at all, while OpenAI at least published a number, even a qualified one, alongside a chip that reached tape-out nine months after its first RTL. Whether that timeline compression from AI-assisted design becomes the industry's next real advantage, rather than a one-project anecdote, is a question only OpenAI's next chip can answer, since Jalapeño is still OpenAI's first clean-sheet accelerator, not its second.