Nvidia Ships a Billion RISC-V Cores, Names None of Them

Nvidia says it shipped about a billion RISC-V processor cores in 2024, embedded inside its own GPUs rather than sold to anyone. The company's own Linux driver documentation for the chip that carries the most important of those cores, the GPU System Processor, never once uses the words RISC-V.

The billion-core number, and whose count it is

The billion-cores-a-year figure comes from Nvidia itself, relayed by RISC-V International, the nonprofit that stewards the open instruction set architecture, so it should be read as a vendor's own tally rather than an independently audited count. Nvidia puts 10 to 40 RISC-V cores inside a single chip depending on its complexity, running more than 30 separate control and management applications on a shared software stack. Frans Sijstermans, Nvidia's vice president of multimedia architecture, laid out the figures at a RISC-V North America summit, according to the same account.

Three designs, none of them for graphics

Nvidia builds three RISC-V core variants, and none of them render a pixel. NV-RISCV32 is a simple in-order design implementing the RV32I instruction set with multiply and user-mode extensions, used for lightweight embedded control. NV-RISCV64 is an out-of-order design with 64-bit addressing, bit-manipulation instructions and multiprocessing support, the variant behind the chip's most important controller. NV-RVV pairs a 32-bit core with a 1,024-bit vector unit built for deep learning workloads. All three plug into what Nvidia calls a Peregrine subsystem: cache, tightly coupled memory, a DMA engine and a crypto block shared across the design.

Core design	Instruction set	Role
NV-RISCV32	RV32I-MU, in-order	lightweight embedded control
NV-RISCV64	RV64I-MSU, out-of-order	GPU System Processor and system control
NV-RVV	RV32 plus 1,024-bit vector unit	deep learning acceleration

The GSP: the core Nvidia won't name

The GPU System Processor is four of those RV64 cores sitting behind a platform-level interrupt controller, with its own memory isolation, a DMA engine and a coherent fabric spanning the whole chip, according to RISC-V International's account of the design. What it does is take initialization, power management and clock control off the driver running on the host CPU and hand it to the GPU itself. Nvidia's own GSP documentation, shipped with its Linux driver, describes exactly that job and confirms the GSP firmware is used by default on every Turing-generation GPU and newer. It does not, anywhere in the document, use the word RISC-V.

Falcon's decade against RISC-V's first year at scale

Nvidia ran its own proprietary microcontroller architecture, called Falcon, for roughly a decade before moving to RISC-V starting around 2016, according to RISC-V International. Falcon shipped 3 billion cores over that entire run. RISC-V passed a third of that total in 2024 alone, on Nvidia's own count. Sijstermans said Nvidia rejected Arm, Synopsys ARC, MIPS and Berkeley's Rocket core before settling on RISC-V, citing Falcon's lack of 64-bit addressing, a data cache, or the ability to run a real operating system.

1. Falcon (approx. 10-year run)3 billion cores
2. RISC-V (2024 alone)1 billion cores

Source: RISC-V International, accessed 2026-09-20

What opening the firmware unlocked, and what it didn't

Nvidia's GSP firmware is closed-source, but the company began letting the open-source Nouveau driver load a signed copy of it, which let Linux users control GPU clock speeds for the first time since roughly the GeForce GTX 700 generation, according to Phoronix's report on the Linux 6.7 merge. Longtime Nouveau maintainer Ben Skeggs wrote the original patches before stepping down from the project, and fellow maintainer Dave Airlie carried the work to completion. Support landed enabled by default only for Ada-generation cards, with Turing and Ampere GPUs requiring a manual driver flag. LWN's coverage of the same milestone reported that Faith Ekstrand's NVK Vulkan driver, once it could reach the reclocking the GSP now exposes, went from 20 frames per second to more than 1,000 on the same test. The firmware itself carries no stable interface. Phoronix reported it works only with the specific Nvidia driver release it shipped alongside, meaning Nouveau has to track Nvidia's own release cadence to keep working, not an open specification Nvidia published once and left alone.

Nvidia's silicon is not the only chip this site has checked against a vendor's own framing. OpenAI's own benchmark claims for its Jalapeño accelerator chip turned out to rest on a comparison the company did not fully disclose, the same asymmetry between a vendor's chosen framing and what an outside party can verify that shows up in Nvidia calling its own embedded processor everything except its instruction set. On the software side, Nvidia has been more forthcoming: it gave developers two ways to write CUDA kernels in Rust, opening a part of its stack that used to be C and C++ only.

What would change this read

Nvidia's core count is real, by its own accounting, and RISC-V International published it under the headline "How NVIDIA Shipped One Billion RISC-V Cores In 2024," using the chipmaker's volume as evidence the architecture has won in scale. None of that has made Nvidia's hardware more open. The firmware stays closed, the interface stays unstable, and the company's own documentation for the chip still will not say what instruction set it runs. A future Nvidia driver README that names RISC-V explicitly, or a stable firmware ABI that frees Nouveau from chasing driver releases, would be the signal that openness reached past the instruction set and into how the chip is actually run.