Inside the Intel 8087: 1,648 Microcode Words, 18 Special-Case Branches and One Add

The Intel 8087 added two floating-point numbers using 1,648 sixteen-bit micro-instructions stored in a read-only memory in the centre of its die, and the add/subtract routine alone spans addresses #0232 to #0298. Ken Shirriff's October 2026 teardown of the chip's microcode walks through that routine step by step.

What the 8087 stored, and how

Intel announced the 8087 in 1980 as a floating-point coprocessor for the 8086, according to Wikipedia's entry. It used about 65,000 transistors on a 4.5 µm depletion-load HMOS process, later shrunk to 3 µm, and shipped at 5, 8 and 10 MHz.

Its microcode ROM packs two bits into each location, read as one of four current levels, which saves die area. The arithmetic follows from Shirriff's count: 1,648 words of 16 bits is 26,368 bits of microcode. A conventional one-bit-per-cell ROM would need twice the cells for the same content.

The 80-bit "temporary real" format has a sign bit, a 15-bit exponent with a bias of 16,383 and a 64-bit significand. Internally, the working register has a 68-bit significand plus guard, round and sticky bits.

How addition works in microcode

Shirriff lays the routine out in eight steps: check for zero operands, subtract the exponents (swapping the operands if needed), shift the smaller operand right to line up the binary points, choose unsigned add or unsigned subtract from the operand signs, run the operation, normalize, adjust precision, and store the result.

The hardware doing this is plain. A 69-bit adder needs two micro-instructions per addition. A 68-bit shifter moves by any amount in either direction. Leading-zero detection runs two 8-input passes, one over bytes and one over bits, which Shirriff notes is simpler than a 64-bit detector though slower.

Component	Size	Role
Microcode ROM	1,648 words x 16 bits	Holds every instruction sequence
Integer adder	69 bits	Two micro-instructions per addition
Shifter	68 bits	Aligns and normalizes significands
Stack registers	8, each tagged	Zero, valid, special or empty

The special-case tax

The number that matters here is not the adder width but the branch count. The common code that runs before every operation contains 18 conditional branches in a row for special values; Shirriff calls it "spaghetti code". Eight of the paths return NaN, covering cases such as zero times infinity and infinity minus infinity in affine mode, and eight return infinity.

Wikipedia says addition and subtraction can take over 100 machine cycles to execute, and some instructions exceed 1,000. Neither source breaks that total down, so how much of it goes to the special-case branches is not established.

The speedup claim and its denominator

Shirriff cites Intel's documentation as putting the 8087's addition speedup over software floating point on the 8086 at almost a factor of 100. Wikipedia quotes a different figure for whole applications: gains "from approximately 20% to over 500%, depending on the specific application." Both can be true. A single add compared with a software routine is a best case; a program that spends most of its time elsewhere sees a fraction of it. A vendor's headline factor deserves the same question today that it did in 1980: speedup of what, against what baseline.

The same habit applies to current robotics specs, for instance Agility's Digit 5 runtime-to-charge ratio, where the headline ratio had no customer measurement behind it.

Cost and legacy

Wikipedia lists suggested unit prices from a 1989 Intel price list.

1. 5 MHz142 USD
2. 8 MHz205 USD
3. 10 MHz270 USD

Source: Wikipedia, Intel 8087, accessed 2026-10-19

The 8087 led to the IEEE 754 standard used today, Shirriff writes, though it did not implement the finished standard in full; that arrived with the 80387, per Wikipedia, because the standard was completed in 1985.

Microcode in a ROM cannot be changed after fabrication, which separates it from firmware in the field; the Broadcom Wi-Fi flaw with no CVE and no patch on Belgian gateways is a reminder of how rarely even updatable firmware gets fixed. What would change this read is a cycle-by-cycle trace of the routine, which Shirriff's post does not give: it lists no per-operation cycle counts, so the over-100-cycle figure rests on Wikipedia alone.