ASML Locks In TSMC and Samsung for a 12-Inch Chipmaking Mask

ASML said Sept. 8 that TSMC and Samsung Electronics have separately committed to its newest High-NA EUV lithography tools, paired with a new, larger photomask format, in two coordinated press releases. TSMC is targeting high-volume manufacturing with High-NA EUV starting in 2030. Samsung said it will bring the same lithography into DRAM production by 2028, which ASML called the first time any chipmaker has committed High-NA EUV to memory manufacturing.

ASML Chief Executive Christophe Fouquet said in the TSMC release that adoption would happen "first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity." TSMC Chairman and CEO C.C. Wei said the collaboration was meant to keep "advanced solutions accessible at scale." In the separate Samsung release, Fouquet added that "Samsung has been one of ASML's most important innovation partners for many years," while Samsung Vice Chairman and CEO Young Hyun Jun said the deal reflects how "the AI era is transforming the semiconductor industry." Neither release named a dollar figure for either company's side of the investment, unusual for announcements of this scale.

Why a photomask needs to double in size

High-NA EUV's higher-resolution optics cut the printable field roughly in half compared with the standard EUV tools chipmakers use today, according to an analysis by FourWeekMBA, forcing manufacturers to stitch multiple exposures together to print a single large die, an expensive process that lowers yield. Moving from the current 6-inch mask standard to a 12-inch format restores enough reticle area that a die can be printed in one exposure again. ASML and TSMC's own release credits the change with removing "stitching constraints" and lowering chipmaking costs, though neither company put a percentage on the savings.

The mechanism behind the shrinking field is optical, not arbitrary. High-NA EUV relies on what Semiwiki's analysis calls anamorphic imaging, demagnifying a pattern differently along the scan direction than across it, which is what shrinks the usable field in the first place. Semiwiki frames TSMC's plan to run High-NA on old 6-inch masks starting in 2030 before moving to 12-inch masks in 2031 as deliberate risk management: it separates "adoption of the new optics from adoption of the new mask infrastructure," so a delay in one does not stall the other.

Company	Use case	High-NA EUV milestone
Intel	Logic (Core Ultra Series 3)	1 million-plus wafers already processed
TSMC	Logic, high-volume manufacturing	Targeting 2030 start
Samsung	DRAM, high-volume manufacturing	Targeting 2028 start, industry first

The timeline is further away than the announcement sounds

Intel Foundry has already processed more than one million wafers using High-NA EUV, across tool certification, R&D and volume production on select layers of its Core Ultra Series 3 chips, according to TrendForce, a Taiwan-based market research firm. That puts Intel's foundry business, which trails TSMC and Samsung commercially, ahead of both on the calendar for this specific tool. Intel's own million-wafer figure spans tool certification, R&D and production on only "select layers" of Core Ultra Series 3, not the full chip, which is a narrower claim than it sounds but still more than either TSMC or Samsung has running today. TSMC's own 2030 high-volume target is still four years out, and it applies to the older 6-inch masks; the 12-inch pilot line the Sept. 8 announcement describes does not arrive until 2031, with full production-ready systems not expected until 2033.

The memory crunch this doesn't fix until 2028

Samsung's DRAM commitment lands in the middle of a memory shortage it will do nothing to relieve for at least two more years. Samsung raised prices on 32GB DDR5 modules from $149 to $239, a 60 percent increase, in September 2025, Network World reported on Jan. 7. Wonjin Lee, Samsung's president and head of global marketing, told the outlet the shortage was "an industry-wide reality," not a Samsung-specific problem, because AI accelerators' appetite for high-bandwidth memory consumes roughly three times the wafer capacity per gigabyte that ordinary DRAM does, pulling fab capacity away from the DDR5 modules used in ordinary servers and PCs.

1. Before increase149 $
2. After increase239 $

Source: Network World, citing Samsung pricing, published Jan. 7, 2026

High-NA EUV is meant to extend the DRAM scaling roadmap by packing more bits into the same die area, which is the long-run fix for exactly this kind of capacity fight. TSMC's own recent price increases on its most advanced logic nodes show the same capacity math playing out one layer up the stack. But 2028 is Samsung's earliest target for High-NA DRAM, and that is only when high-volume manufacturing begins, not when the resulting chips reach a system like the 192GB workstation configurations that already strain under today's memory prices. What would change this read is either company moving a date forward, or a third memory maker announcing a High-NA DRAM timeline that undercuts Samsung's 2028 target. Nothing in Tuesday's releases suggests either is coming. For now, the fix and the shortage it is meant to eventually address are simply running on different clocks.