AMD's 256-Core EPYC 9996 Has 16.4 ns L3 Latency; the 96-Core 9686F Has 10.7 ns

The headline number for AMD's Zen 6 server chips is 256 cores, but the figure that separates the two core designs is L3 latency: 10.7 ns on the standard Zen 6 core and 16.4 ns on the dense Zen 6c core, according to Chips and Cheese's November 10, 2026 teardown by George Cozma. The part that carries 256 cores, the EPYC 9996, is the slow-cache one.

The two EPYC 9006 parts compared

AMD's list for the EPYC 9006 "Venice" family, summarised by StorageReview's Brian Beeler on September 26, 2026, gives the flagship EPYC 9996 256 cores and 512 threads, a 2.55 GHz base clock, a 4.1 GHz maximum boost and 1,024 MB of L3. The frequency-optimised EPYC 9686F has 96 cores, a 3.4 GHz base, a 5 GHz boost and 384 MB. Both use the SP7 socket with 16 channels of DDR5.

	EPYC 9996 (Zen 6c)	EPYC 9686F (Zen 6)
Cores / threads	256 / 512	96 / 192
Max boost	4.1 GHz	5 GHz
L3 cache	1,024 MB	384 MB
1Ku price	$14,904	$11,434

Chips and Cheese reports that the 9686F is built from 12-core chiplets and the 9996 from 32-core chiplets, with 4 MB of L3 per core on both: 48 MB per 12-core chiplet and 128 MB per 32-core chiplet. Eight of each gives the 96-core and 256-core totals, which is arithmetic from the two sources and not a figure either states.

Why the cache latency gap matters

On the Zen 5 EPYC 9355P, Cozma measured L3 latency of about 47 cycles, or 10.3 ns. Zen 6 comes in at about 55 cycles, 10.7 ns; Zen 6c at about 66 cycles, 16.4 ns.

1. Zen 5 (EPYC 9355P)10.3 ns
2. Zen 610.7 ns
3. Zen 6c16.4 ns

Source: Chips and Cheese, George Cozma, Nov. 10, 2026

The dense core pays for its scale with a farther cache, then offsets it inside the core. Per Chips and Cheese, the reorder buffer grows from 576 entries on Zen 6 to 640 on Zen 6c, the integer register file from 288 to 352, the vector scheduler from 138 to 180 and the load queue from 280 to 330. A bigger out-of-order window hides more memory delay; Cozma's conclusion is that Zen 6 looks tuned for high frequency while Zen 6c has more capacity to tolerate memory latency.

The delivered result is close. In Chips and Cheese's estimated SPEC CPU 2026 single-thread runs, the 9686F scores 6.20 integer and 10.6 floating point; the 9996 scores 5.25 and 8.99. At a matched 4.1 GHz, the 9686F scores 4.92 integer and 8.64 floating point, so per clock Zen 6c is about 6.7% ahead in integer and 4% in floating point. The old EPYC 9575F scores 5.13 and 9.01 while running about 900 MHz faster than the 9996, which means the new dense core matches last generation's frequency part at lower clocks. These are estimates by a third party, not SPEC-published results.

What changed inside the core

Zen 6 gains 64 bytes per cycle of L2 read bandwidth, up from about 42 on Zen 5. Integer throughput reaches 5.96 64-bit adds per cycle against 5.25 on Zen 5, both with six ALUs, and 512-bit VNNI rate doubles from 1.99 to 3.88 instructions per cycle. Integer multiply units fall from three to two, and the floating-point units stay at two 512-bit units.

AMD's own claims sit apart. Its July comparison put the 9996 against Intel's 128-core Xeon 6980P, priced at $13,955 by AMD, on the SPECrate integer suite; StorageReview notes the 9996's $14,904 price matches the figure AMD used there. AMD has also replaced TDP with "Default CPU Power", defined as total power across compute and I/O dies, 600 W for the 9996 and 500 W for the 9686F. Treat all of AMD's comparative figures as vendor-supplied.

Related coverage on the compute that these chips feed includes Anthropic's Fable 5.2 pricing and Meta's Muse Ember pricing and closed weights.

Memory bandwidth per core is the second denominator

Both parts share the SP7 socket's 16 DDR5 channels, which StorageReview rates at 1,024 GB/s per socket with 8,000 MT/s RDIMMs and 1,638 GB/s with 12,800 MT/s MRDIMMs. Divide by core count and the picture changes: 1,024 GB/s across 256 cores is 4 GB/s per core on the 9996, while the same pipe across 96 cores is about 10.7 GB/s per core on the 9686F. The same arithmetic with MRDIMMs gives about 6.4 and 17.1 GB/s. These are peak ratings divided by core counts, not measured bandwidth.

That is why the 128 MB per 32-core chiplet matters: a workload that spills out of L3 on the 9996 competes with 255 other cores for the same memory channels, and a longer L3 path makes the spill start sooner. AMD's product pages list PCIe 6.0 x96 for the socket, which StorageReview reports, and the same I/O is shared by both parts.

What would change this read

StorageReview reports that systems on the SP7 platform are expected in the fourth quarter of 2026, and that Giga Computing expects them to ship with AMD's November launch. Neither source states the process node or confirms shipping volumes. The buyer's question is a denominator one: price per core is $58 on the 9996 and $119 on the 9686F, from the list prices above, but a workload that stalls on cache loses the per-core advantage. Independent whole-chip benchmarks, not single-thread estimates, are the evidence that would settle it.